ACA1233n registers

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General

The ACA1233n is the 2016-incarnation of our 128MByte-MC68030 accelerator. It makes a number of small changes:

  • memory is now autoconfig, so even Kickstart V3.0 users have full memory from a cold start without the ACAtune tool
  • MapROM is now activated with a different tool, ACAMapRom
  • Chipram access speed has been improved
  • A1200-IDE access speed has been improved
  • improved Fastmem write speed
  • FPU option (at the customer's risk - operation guaranteed only without FPU)
  • 1MB MapROM option
  • operation as 9MByte memory expansion on A1200 (68030 disabled)
  • can be completely disabled for highest compatibility with floppy-based games

Autoconfig

The ACA1233n uses Z2/Z3 Autoconfig through the Z2 config window $00e8.0000. Vendor ID $1212 and product ID 33 ($21) are used in 68030 mode. In 68ec020 mode, product ID 32 is used. The physical board size in 68030 mode is 128MByte. Subsize is "auto-sized", which results in a single 126MByte block starting at address $4000.0000. In Z2 mode, the board size is 8MByte (regardless of selected CPU).

Older versions of the card use autoconfig ID 68 ($44) in 68030 mode, and ID 72 ($48) in 68ec020 mode. These cards have a non-working "NoMemcard"-bit. All other features are fully working. Customers can get a free CPLD update at any time.

The serial number of the Autoconfig board shows the CPU clock in MHz, rounded down to a whole number (for example the 26.667MHz version will show 26). The serial number will remain the same, regardless of the selected CPU.

Cards shipped after july 2019 have added features that are indicated by a serial number that's increased by 128. This means that the 55MHz card shows serial number 183.

memory map

Memory areas not shown will access the host computer.

address range description
$00c0.0000 to $00cf.ffff 1MB Fastmem
$00e0.0000 to $00e7.ffff 512KB ROM or mapped Fastmem, depending on MapROM bit
$00f8.0000 to $00ff.ffff 512KB ROM or mapped Fastmem, depending on MapROM bit
$01e0.0000 to $01e7.ffff 512KB ROM regardless of MapROM register
$01f8.0000 to $01ff.ffff 512KB ROM regardless of MapROM register
$4000.0000 to $47df.ffff 126MB Fastmem
$47e0.0000 to $47e7.ffff 512KB empty space
$47e8.0000 to $47ef.ffff ACA1233n register space
$47f0.0000 to $47f7.ffff 512KB lower MapROM space (will show in $00e0.0000 when enabled)
$47f8.0000 to $47ff.ffff 512KB upper MapROM space (will show in $00f8.0000 when enabled)

register space

Register bits of the ACA1233n are written to by writing any value to a given set or reset location (byte or word access only, long-access will hit the next location!). Note that the register locations are different for 68030 and for onboard-68ec020 operation.

For reading register contents, the upper nibble (data bits 12-15) of a word location are valid. For writing, you can use any value, as the written data is not used at all. For clarity reasons (code maintainability), please write 0 to a reset location and write 1 to a set location.

set (68030) reset (68030) set (68ec020) reset (68ec020) bit description 26MHz card 40MHz card 55MHz card 40MHz (Jul-2019) 26MHz (Jul-2019)
$47e8.f000 $47e8.f020 $b8.f000 $b8.f020 unlock bit 0
$47e8.f002 $47e8.f022 $b8.f002 $b8.f022 unlock bit 1
$47e8.f004 $47e8.f024 $b8.f004 $b8.f024 unlock bit 2
$47e8.f006 $47e8.f026 $b8.f006 $b8.f026 unlock bit 3
$47e8.f008 $47e8.f028 $b8.f008 $b8.f028 MapROM bit
$47e8.f00a $47e8.f02a $b8.f00a $b8.f02a Z2 compatibility bit
$47e8.f00c $47e8.f02c $b8.f00c $b8.f02c Clock divide enable
$47e8.f00e $47e8.f02e $b8.f00e $b8.f02e Clock divisor bit 0 ✓✓✓ ✓✓✓ ✓✓✓
$47e8.f010 $47e8.f030 $b8.f010 $b8.f030 Clock divisor bit 1 ✓✓ ✓✓ ✓✓
$47e8.f012 $47e8.f032 $b8.f012 $b8.f032 NoMemcard ✓+ ✓+ ✓+
$47e8.f014 (none) $b8.f014 (none) CPU switch trigger
$47e8.f016 $47e8.f036 $b8.f016 $b8.f036 set # of Write-waitstates
$47e8.f018 $47e8.f038 $b8.f018 $b8.f038 No C0 mem
(none) (none) $b8.f01a $b8.f03a Ramdisk overlay
(none) (none) $b8.f01c $b8.f03c Ramdisk Bank shift register

Legend: ✓: Register is available. ✓+: Register has improved function on new cards ✓✓(✓): Register has double/triple-meaning, see explanation. ○: Register is not available.

locking and unlocking

Writing to any other register than the unlock registers is inhibited after a reset. Reading any of the unlock bits will set all unlock bits to 0, which means that registers are locked. Registers are "unlocked" when unlock bit 3 is 1. You cannot set this bit directly to 1, but need to follow this sequence:

  • set unlock bit 0
  • set unlock bit 1
  • reset unlock bit 0
  • set unlock bit 2
  • reset unlock bit 1
  • set unlock bit 3

After the last write access, the other registers become writable. Read from any unlock bit address to lock registers again.

MapROM bit

This bit is 0 after every power-up. It is not changed on a reset. If set to 1, the Kickstart ROM of the host computer is replaced with Fastmem from locations $47f0.0000 and $47f8.0000.

The $01e0.0000 and $01f8.0000 areas have been introduced to give software a possibility to switch MapROM off: If you find that these ROM areas are identical with the mapped ROM areas, it is safe to switch off MapROM while the system is running. If the areas are different, a reset is required right after setting MapROM=0.

Z2 compatibility bit

This bit is 0 after power-up and does not change it's content with a reset. Set this bit to 1 if you intend to use a Kickstart ROM version that does not support Z3 autoconfig (V1.3 or earlier). The autoconfig nibbles will be changed to represent an 8MByte card in Z2 memory space starting at $0020.0000. You can still use the memory outside the lower 16M space, and $00c0.0000 memory is also still available, so the computer will show 9 MBytes of usable fastmem from a cold-start.

Memory in 32-bit area still starts at $4000.0000. Since the memory in Z2 space is taken from the last 14MBytes of the 128MB-chunk, you should only add 114MBytes from $4000.0000 to $471f.ffff to the freemem pool. If required, another 4 MBytes of memory can be added to the freemem pool from $47a0.0000 to $47df.ffff. Caution: Memory between $4720.0000 and $479f.ffff is a mirror of $0020.0000 to $009f.ffff. It is not write-protected, but it appears twice in memory space if the Z2 compatibility bit is set to 1.

After setting the bit to 1, a system reset should be executed.

New feature in cards shipped after July-2019: For testing low(er) memory conditions or keeping the PCMCIA port enabled, you can reduce the Z2 autoconfig size to 4MB by clearing Clock divisor bit 0. The complete 8M memory chunk starting at $0020.0000 is still available, but only 4M will be added by autoconfig, keeping the PCMCIA port active for networking cards (not for memory cards!). The rest of the memory can be added later (if desired).

Clock divide enable

Setting this bit allows reducing the card's power consumption by reducing the CPU clock and memory access speed. In detail, the following changes to normal full-speed operation are applied:

  • syncronous access termination is disabled - only 68020-like DSACKx termination is used
  • Cache burst accesses (both instruction and data) are switched off, but cache remains active
  • chipram access speed is reduced to standard asyncronous speed
  • CPU clock divider is activated, allowing these four CPU clock rates:
divisor bit 1 divisor bit 0 resulting speed 26/40MHz card resulting speed 55MHz card
0 0 13.33 MHz 11.11 MHz
0 1 16.00 MHz 13.89 MHz
1 0 20.00 MHz 18.52 MHz
1 1 26.67 MHz 27.78 MHz

55MHz card additional bit meanings

On the 55MHz card, the two clock-select bits have more uses. If the card runs at full speed (CPU clock divider disabled), Divisor bit 0 will switch on a more aggressive timing for chipram and IDE access: This is "on the edge" for PAL-clocked machines with a base clock of 28.37516MHz, and it will be "just right" for NTSC-clocked machines with a base clock of 28.63636MHz. The performance of 7.1MB/s cannot be changed, but the number of CPU cycles between accesses may be higher if this bis is set. Use with caution; if you are getting R/W errors on your IDE drives, please set back to 0. Further, Divisor bit 0 has an influence on the Z2 autoconfig zize: The reported size will be 4MBytes for Divisor bit 0=1. Since the autoconfig nibbles will only be read once after a reset, changing the state of this bit in operation will only affect the board access timing.

Divisor bit 1 will enable high-speed access to the IDE data registers. Only use with IDE devices that support PIO mode 4 or higher. The raw data transfer performance will be increased to 11.3MB/s, which results in every-day performance of 5.5MB/s with average CF cards. This speed beats the performance of our original IDE-fix express product, which is not made any more. If a 4-way IDE interface is installed in the computer, both IDE ports will be accelerated.

40MHz cards after july 2019 additional bit meanings

On all 40MHz cards shipped after july 2019, the two clock bits have more uses - very similar, but not identical to the 55MHz card. Setting Divisor bit 1 will enable high-speed access to the IDE data registers. Only use with IDE devices that support PIO mode 4 or higher. The raw data transfer performance will be increased to 10.9MB/s (12.7MB/s on higher-speed reads), which results in every-day performance of 4.5MB/s (4.8MB/s on higher-speed reads) with average CF cards. This speed beats the performance of our original IDE-fix express product, which is not made any more. If a 4-way IDE interface is installed in the computer, both IDE ports will be accelerated. With high-speed IDE access enabled, setting Divisor bit 0 will enable higher-speed reads. This will only work reliably with solid state media, but most likely not with real harddisks that are connected with a cable. If you get checksum errors on your harddisk, please switch back to the "slower" accelerated IDE speed by resetting Divisor bit 0 to 0. Note that both timings are compliant with PIO mode 4, but propagation delays of bus drivers, the cable and last not least the A1200 mainboard will take their toll on data arriving in time for the CPU to pick them up.

Further, Divisor bit 0 has an influence on the Z2 autoconfig zize: The reported size will be 4MBytes for Divisor bit 0=1. Since the autoconfig nibbles will only be read once after a reset, changing the state of this bit in operation will only affect the IDE read access timing.

26MHz cards after july 2019 additional bit meanings

On all 26MHz cards shipped after july 2019, the two clock bits have more uses - very similar, but not identical to the 55MHz card. Setting Divisor bit 1 will enable high-speed access to the IDE data registers. Only use with IDE devices that support PIO mode 3 or higher. The raw data transfer performance will be increased to 8.5MB/s (10.2MB/s with PIO mode 4), which results in every-day performance of 3.4MB/s (3.6MB/s with PIO mode 4) with average CF cards. This speed beats the performance of our original IDE-fix express product, which is not made any more. If a 4-way IDE interface is installed in the computer, both IDE ports will be accelerated. With high-speed IDE access enabled, setting Divisor bit 0 will enable PIO mode 4. This will only work reliably with solid state media, but most likely not with real harddisks that are connected with a cable. If you get checksum errors on your harddisk, please switch back to PIO mode 3 by resetting Divisor bit 0 to 0. Note that although your harddisk may support PIO mode 4, propagation delays of bus drivers, the cable and last not least the A1200 mainboard will take their toll on data arriving in time for the CPU to pick them up.

Further, Divisor bit 0 has an influence on the Z2 autoconfig zize: The reported size will be 4MBytes for Divisor bit 0=1. Since the autoconfig nibbles will only be read once after a reset, changing the state of this bit in operation will only affect the IDE read access timing.

NoMemcard bit

For all cards shipped before july 2019, this bit only has a meaning for 68ec020 operation: It will switch between 9M of memory with NoMemcard=0 and 0M of available memory with NoMemcard=1. Starting with cards shipped after july 2019, the NoMemcard bit will not touch the 1M memory chunk at $00c0.0000 any more. If the NoMemcard bit is set in Z3 mode, Z3 auto-configuration will still be active, but the nibbles will be changed to tell the OS to not add the memory to the free memory pool. This allows you to reduce the system for test/compatibility reasons: With $c0 memory active, you'll have 1M Fastmem plus chip ram, and with $c0 memory disabled, you'll have a chipram-only system.

switching CPUs

The ACA1233n allows switching between the two available CPUs: The 68ec020 CPU located on the A1200-motherboard and the 68030 CPU located on the accelerator. Writing any value to the trigger location will switch from 68030 to 68ec020 or vice versa, then cause an immediate hardware reset. This will also lock all registers.

The card will come up with the 68030 CPU on a power-up. When switching to 68ec020, the user can choose whether additional fast memory shall be available or not. If the NoMemcard bit is set and 68ec020 is chosen, the ACA1233n will be switched off completely. If the NoMemcard bit is 0 and 68ec020 is chosen, then 9MBytes of fast memory will be available: 8MByte as a Z2-autoconfig card and 1MByte in $c0.0000.

Cards with a serial number >128 have the added possibility to configure 4MBytes, 5MBytes, 8MBytes or 9MBytes memory configurations for 68ec020 operation. This will let developers test low(er) memory conditions for newly-developed software that shall work on a larger variety of A1200 configurations.

number of write-waitstates

The SD-Ram controller of the ACA1233n can be configured to operate with 0-waitstate or with 1-waitstate. Write performance is significantly higher with 0-waitstate, but timing is very tight and may get instable if an FPU is installed, the power supply is not absolutely stable or environmental conditions are difficult for the card (e.g. excessive heat). Timing on power-up will be set to 0-waitstate if there is no FPU installed, and it will be set to 1-waitstate if an FPU is installed. This bit can be set/reset at any time, regardless of FPU presence, so you can also try if the computer is stable with FPU and 0-waitstate for writes. The effect of this bit is instant, and it's value does not change on a reset. This register is not present on the 55-MHz and 26-MHz cards, because the RAM controller runs at a different speed. Write performance is always optimal on these cards.

No C0 mem

This bit is 0 after a power-up and does not change it's contents on a reset or CPU switch. Set this bit to switch off memory in $00c0.0000. This is either useful for compatibility with old software, or for compatibility with DMA devices that use the lower 16M address space (for example the A2091 or GVP SCSI controllers). This bit works in both 68030 and 68ec020 modes. Caution: The effect of this bit is instant, and you might switch off the memory area where stack is located. For switching off this memory area, it is recommended to forbid multitasking and execute a reset or CPU switch right after setting the "No C0 mem" bit. Further, it will be required to make the system re-check for availability of $c0 memory.

Ram disk function

This function can only be activated in 68ec020 mode. If the Ram disk overlay bit is set, the 2MByte Chipram space is replaced with a 2MByte window from the 128MByte physical memory space. Naturally, you should switch off multitasking before setting this bit, and your code should run outside the 2M Chipram area. For accessing the whole 128MByte space, a total of six banking bits are required. These are arranged in a shift register that you can write to through locations $b8.f01c (set) and $b8.f03c (reset). Writing to one of these two locations will set/reset banking bit 21. At the same time, the previous contents of banking bit 21 will be shifted left into banking bits 22 to 26. If for example you want to access the very last bank of Fastmem, you just need to write six times to $b8.f01c. If the Ram disk overlay bit is now set, you will find the MapROM space in $10.0000.

Caution: The Z2 memory space from $20.0000 to $9f.ffff will also be accessible through this function, and it will NOT be write-protected. Software must make sure that banks 02 to 05 are not accessed. The mirror of the $c0.0000 memory window will be write-protected, and the 1MByte MapROM space will also be write-protected if the MapROM bit is set to 1.

The Ram disk overlay bit and the six banking bits are set to 0 on a reset, power-up or CPU switch. Make sure to switch off the Ram disk enable bit before re-enabling multitasking.

Please note that the Ram disk function has been removed on the 55MHz version in order to fit other optimizations. There is no software that uses this function, and it is unlikely that we'll ever make any. The reason is that such a RAM disk can only be used if the OS is active. Programs would access this RAM disk through OS functions, so they would be written in a way that they'd also work with the 68030 CPU, hence the normal Ram disk could be used.

reading register contents

4k register space is reserved for reading back the current register bit values, where the given two locations are mirrored over the whole space. For future compatibility, you should only use the exact addresses in the following table, as other locations may contain other data in a future version. Note that these locations have nothing to do with the set/reset locations. Reading the registers is possible at any unlock state. Note that reading one of the unlock bits will not only lock write access to any register bit, but also return one of the two read-windows:

68030 read location 68ec020 read location bit 15 bit 14 bit 13 bit 12
$47e8.f008 $b8.f008 MapROM Clock div 0 Clock div 1 Clock divide enable
$47e8.f00a $b8.f00a Z2 mode NoMemcard write-wait states No C0 mem

The Ram disk overlay bit and the banking shift register contents cannot be read. Bit locations refer to a word-access. You may also do a byte-read of the given address, then the bit locations will be 7 down to 4.

Software considerations

using MapROM with 68ec020 CPU

The 1MB MapROM function can also be used if the 68030 CPU is switched off. There are two possibilities to acticvate MapROM: You can use the 68030 CPU to prepare the memory and set the MapROM bit before executing the switch to 68ec020. If the computer is already in 68ec020 mode, you can write to the required memory space by using the Ramdisk banking function. The NoMemcard bit must be 0, as memory where the Kickstart ROM comes from, must be available (doh!). The 1MB MapROM option does not affect the amount of available fastmem with any CPU.

operation on ACA500 and ACA500plus

The memory card function is only available in A1200s. If the ACA1233n is used on an ACA500 or ACA500plus, it will always have the "NoMemcard" bit is set. It is still possible to switch from 68030 to 68ec000, but you cannot switch back. There is no possibility to make RAM accessible for the 68ec000 of the ACA500. You probably don't need this feature on the ACA500plus, as it already comes with lots of memory.

$b8.f0xx register space

This register space is also active if the "NoMemcard" bit is set. There may be two reasons to access the register bits: Switching CPUs or re-activating the Memory card function. Without Autoconfig (which is also switched off with the NoMemcard bit), you have no way of identifying the card. You can still safely attempt a CPU switch or switching on the memory card function, as going through the unlock sequence and writing to registers will not do any harm on a computer that is not equipped with the ACA1233n.

A "soft marker" for presence of the ACA1233n is that bits 0-11 of the $b8.fxxx area are 1 on a read. If you do not find $xfff on a word-read, it's a hard marker for non-presence.

clean CPU switching

When switching CPUs with a commandline or GUI tool, please make sure that all harddrive operations have completed. Accessing the CPU toggle register may cause an immediate reset, so any buffers not yet written to a harddrive will be lost. The "reset warning" mechanism from big box Amigas may be a good role model.

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