BuddhaPlusOneRegisters

Buddha Plus One register map

Autoconfiguration data:

Vendor number: 4626 ($1212)
product number: 0
Serial number: 6 (indicating the 2023 "Plus One" version)
Rom-vector: $1000

The card is a Z-II board, size 64K, not for freemem list, Rom-Vector is valid, no second Autoconfig-board on the same card, no space preference, supports "Shutup_forever". Caution: The indication to support "shutup forever" has been added to the config nibbles for backwards compatibility. Since the feature has never been used over the history of the Amiga, it has been optimized out of the logic in favour of new features. Backwards compatibility was a major goal of this developmoent, because there are drivers available for AmigaOS, Linux and BSD that will most likely be compatible with the new hardware without any change.

Setting the base address should be done in two steps, just as the Amiga Kickstart does: The lower nibble of the 8-Bit address is written to $4a, then the whole Byte is written to $48, while it doesn't matter how often you're writing to $4a as long as $48 is not touched. After $48 has been written, the whole card disappears from $e8 and is mapped to the new address just written.

Note that the Autoconfig nibbles are also stored in the EEPROM, so in theory, the vendor number, product number and ROM vector can be changed in the field.

The local memory-map is even active when mapped to $e8:

Address	Description
$0-$7e	Autoconfig-space, see Z-II docs.
$80-$7fe	reserved; could be used for additional ROM space
$800-$8ff	IDE-Select 0 (Port 0, Register set 0)
$900-$9ff	IDE-Select 1 (Port 0, Register set 1)
$a00-$aff	IDE-Select 2 (Port 1, Register set 0)
$b00-$bff	IDE-Select 3 (Port 1, Register set 1)
$c00-$cff	CF card Select 0 (CF card slot Register set 0)
$d00-$dff	CF card Select 1 (CF card slot Register set 1)
$e00-$eff	local clock port
$f00	read only: Bit 7: IRQ-line of IDE port 0. Bit 6: 1=Ram enabled. Bit 5: Always 0
$f02	read only: Bit 7: IRQ-line of IDE port 0. Bit 6: 1=Ram addr=$c0.0000, 0= Ram addr=$a0.0000. Bit 5: Always 1
$f40	read only: Bit 7: IRQ-line of IDE port 1. Bit 6: Always 0. Bit 5: Always 0
$f42	read only: Bit 7: Coldstart. Bit 6: 1 when write-lockdown active. Bit 5: Always 1
$f80	read only: Bit 7: Always 0 (for CF card IRQ). Bit 6: Always 0. Bit 5: Always 0
$f82	read only: Bit 7: EarlyWrite. Bit 6: Always 0. Bit 5: Always 1
$fc0	write: Any value written to this register enables IRQs to be passed from the IDE ports to the Zorro bus. read: Bit 7: Always 1. Bit 6: Always 0. Bit 5: Always 1
$fc2	write: Access to mode bits (see further down) read: Bit 7: Fast-Z2 mode. Bit 6: Always 0. Bit 5: Always 1
$1000-$ffff	Buddha-Rom with offset $1000 in the rom chip. The addresses $0 to $fff of the rom chip cannot be read. Rom is Byte-wide and mapped to even addresses.

The IDE ports issue an INT2. You can read the level of the IRQ-lines of the IDE-ports by reading from the two registers $f00 and $f40. Bit#7 of read-register $f80 has been set to a fixed value, indicating that there is no IRQ pending from a third IDE port; this has been done for compatibility reasons.

Note that Bit#5 is always 1 on read-accesses from addresses ending in 2, while it is always 0 on read accesses from addresses ending in 0. This can be used as an indicator for the new "Plus One" hardware.

The IDE ports are fed by the address lines A2 to A4, just as the Amiga 1200 and Amiga 4000 IDE ports are. This way existing drivers can be easily ported to Buddha. A move.l polls two words out of the same address of IDE port since every word is mirrored once. Use address offset $40 to indicate that you are accessing a command register; the controller will adapt it's timing accordingly if this address offset is used. movem can be used by accessing address offset $80 to the IDE register spaces. This will work with all of the six IDE/CF card registers: The Data port register will be mirrored over the whole address space, for example $0c80 to $0cbe. IDE address offset $c0 to $fe will not generate any access to IDE/CF devices at all. This accommodates for a bug in the 68000 CPU that is not explained any further in this register description.

EEPROM banking

The EEPROM chip on the Buddha Plus One has 64kBytes capacity. However, only the one half is accessible at a time. After a reset or cold start, Bank#0 will be selected by the hardware. To switch to bank#1, execute a byte-write of $00 to odd address byte offset $00c3. To switch back to bank#0, execute a byte-write of $00 to odd address byte offset $00c1. Please note that this will also switch the autoconfig nibbles at offset $0000, because these are also located in the EEPROM. Don't let this confuse you - just take advantage of the added EEPROM space.

Coldstart bit

This bit is set to 1 on a cold start and has been introduced to indicate that the computer has just been switched on. Use it to determine if the mode bits (see further down) need to be updated from the flash config or not. Once you've run your initial-startup routine, set this bit to 0 by writing $60 to offset $0f42. This write access will work without any preparation (no unlock/enable sequence required). Note that this write access looks like it's affecting other bits, too, but that is not the case. Read and write registers of this controller are somewhat separated for historical/compatibility reasons.

Buddha Plus One mode bits and 1Mbyte memory option

Mode bits are accessible through the $0fc2 register. Access to these bits is normally inhibited and must be enabled first by executing the following four write accesses:

• write $00 to card offset $0fc2
• write $a0 to card offset $0fc2
• write $50 to card offset $0fc2
• write $a0 to card offset $0fc2

After this sequence, the following writes will actually have an effect. Note that the writes must be executes with byte-writes only, and they Must be done in the exact order shown here:

enable Fast-Z2 mode on Z4 board

• write $b0 to card offset $0fc2

disable Fast-Z2 mode on Z4 board

• write $30 to card offset $0fc2

Enable 1MByte fastmem at $a0.0000

• write $70 to card offset $0fc2
• write $60 to card offset $0fc2

Enable 1MByte fastmem at $c0.0000

• write $c0 to card offset $0fc2
• write $60 to card offset $0fc2

Disable 1MByte RAM expansion

• write $70 to card offset $0fc2

Activate early write mode for command accesses

• write $90 to card offset $0fc2

Deactivate early write mode for command accesses

• write $80 to card offset $0fc2

or

• write $f0 to card offset $0fc2 (this is a safety measure, see EEPROM write mode)

EEPROM write mode

• write $f0 to card offset $0fc2

This will hide all IO registers of the Buddha (including the $0fc2 register) and fill the complete 64k autoconfig space with the EEPROM, only using even addresses. For properly talking to the EEPROM, please consult the 29EE512 datasheet from SST. EEPROM write mode will give you access to all addresses of the chip, because banking accesses also work in this mode. In theory, you can even use the normally-invisible (shadowed by IO registers) space from $0800 to $0ffe. Since this area is available twice (two banks of the chip), this gives an additional 1KByte of EEPROM space.

If write lockdown is selected, then EEPROM write mode can still be activated. You will lose the IO area and have full read access to the chip, including banking, but no write accesses will be generated for the flash chip.

To end EEPROM write mode, execute a byte-write of $00 to odd address offset $0001.

Lockdown EEPROM write

• write $e0 to card offset $0fc2

This will inhibit command $f0 to activate EEPROM write mode. This setting will remain active until the next reset. This behaviour is different from the previous 20-year anniversary edition of the Buddha, and it will increase user-friendliness when trying to update/flash the controller with a new version, as no immediate user actions are required after a cold start. On the other hand, this decision makes it necessary to inhibit EEPROM write mode on every autoconfig if the user did not explicitly choose to keep the chip write-enabled for an update.

End access to Buddha Plus One mode bits

• write $00 to card offset $0fc2

or

• byte-write $00 to odd card offset $0001

Reset behaviour of mode bits

RAM settings will survive a reset, so the memory is fit for resident structures. Please note that whatever address you select for the RAM address, the speed will always be full fastmem speed of a 68000 CPU. Even if the trapdoor space $c0.0000 is selected, a maximum-bitplane hires screen will not slow down access to this memory space. Further, the $a0.0000 space is normally a CIA register mirror on an A2000, and it is listed as "extended IO area" on A3000 and A4000 systems. Hence, it is expected that accelerator caches are not enabled for this memory area, and most likely can't be enabled at all, as caches are usually disabled by the hardware, not by a software setting. While on a plain 68000 system, the memory will appear like full-speed fastmem, it's speed will be low compared to accelerator-based fastmem, and it's priority should be chosen accordingly.

Fast-Z2 and early write mode will also survive a reset. This is to support the GUI in "use" and "save" options: The user can attempt to switch one or both of these modes on, and see if the system still boots. However, the user should be prompted with a warning that a power cycle will be required to switch back to normal Z2 operation if something does not work.

A reset will end access to mode bits, so accidental writes won't happen. A new enable-process must be executed with the 4-byte write sequence to $0fc2 as outlined above.