X-Surf-100

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X-Surf 100

X-Surf-100 is the successor to our Ethernet card X-Surf. As the name indicates, it is a 100MBit Ethernet card.

X-Surf-100 is a Z2/Z3 auto-sensing card: In an Amiga 2000, it will work as a Zorro-2 card. In an A3000 or A4000 computer, it will work as a Zorro-3 card. For stable operation, a Buster-11 chip is recommended. Proper function is only guaranteed in original Commodore daughterboards. The X-Surf-100 may or may not work in second-source daughter boards like Elbox, RBM or Eagle. Should you experience instabilities, you can close the jumper on your X-Surf-100, which will force the slower Z2 mode, even in Z3 computers. This may or may not give you stable operation in daughter boards that are not fully Zorro-compliant.

Contents

Software download

special turbo versions for AmiTCP/Genesis included, debug versions included

operation under OS3.x

The X-Surf-100 comes with a Sana-II device only. Before you can run programs on the Amiga that make use of a networking card, you must install a TCP/IP stack. Choices for the classic Amiga OS are:

  • Miami (not sold any more)
  • Miami Deluxe (not sold any more)
  • AmiTCP
  • Genesis
  • Roadshow

Miami and Miami Deluxe are not sold any more, and if you already own one of these stacks, you will probably just exchange your old sana-II device with the x-surf-100.device. Roadshow is a commercial product still available today, but since it does not reach the speeds that AmiTCP/Genesis can reach, we will only describe Genesis here.

Genesis is a graphical front-end for AmiTCP, which is included in the Amiga OS3.9 package. TODO: Describe how to install and tweak AmiTCP for highest speeds.

operation under NetBSD

You can find a NetBSD driver here

Note that this driver is a 3rd-party development. It was funded by iComp, but please understand that we cannot give support for this driver.

compatibility with other Z3 cards

Mediator Z3

For compatibility with Mediator Z3, please set the "swap config" jumper on the logic board of Mediator. This will free enough Z3 address space for your X-Surf-100.

Merlin

Please make sure you're using the latest hardware revision that has IC13 and IC14 removed, IC24 and IC25 with the latest firmware and some wire patches on the solder side of the card. Further, you way want to add the "reset-fix" to the Merlin, consisting of two diodes and a resistor. In any case, proper function of the X-Surf-100 with the Merlin in Z3 mode may be critical, and you may need to put the Merlin into Z2 mode to get all your boards compatible.

register level description

X-Surf-100 uses autoconfig(TM). It will identify with these values:

  • Vendor ID: 4626 (individual Computers)
  • product ID: 100 (X-Surf-100)
  • Z2 size: 64k
  • Z3 size: 64M, subsize 64k
  • supports "shutup forever"
  • Serial number 12 for release-candidate units (shipped after august 12th, 2013)
  • Serial number 9 for later beta-units units, which should get a logic update
  • Serial number 8 for prototype/beta-units, which should get a logic update

The config-nibbles will disappear right after the config process has been completed and an address has been assigned to the card. During the autoconfig-phase, peripheral chips are not available. After the card has been configured, the following memory map is used. Please treat all addresses that are not described here as "reserved" and do not access them. The board does not only support "shutup forever", but also goes into shutup-mode automatically if an address above $8000.0000 is assigned in Z3 mode. Drivers should warn the user if the board is found at an address above or equal to $8000.0000.

  • $0040: network IRQ status. Word or byte access, read-only. Bits 15 shows the status of the Ethernet IRQ line: 1=IRQ is active, 0=no IRQ2 from this card. When porting a driver from the predecessor X-Surf, please make sure that the driver only looks at this bit, but not at bit#13, which was a copy of bit#15 on the old card. Byte-access to this register is also allowed - the bit to look at would then be #7. All other bits in this register are undefined and should be masked out. This register has mirrors in all addresses of the card where the bit pattern of the address matches %0xxx0xxxx1000000.
  • $0800-$087C: AX88796B Ethernet chip, standard registers. Read/write word access only. This chip is mostly NE2000-compatible. Register spacing is 4 bytes (as opposed to 2 bytes on the old X-Surf card). This register-area is byte-swapped, so little-endian data can be used by the big-endian architecture of the Amiga.
  • $0880-$08FC: The NE2000 data port, which normally only occupies addresses $0840, is mapped to these registers. This area uses 0-waitstate in all cases and may therefore be faster than the longword-area (see further down).
  • $0900-$0FFC: mirror of AX88796B area (includes Fifo area)
  • $1800-$1FFC: AX88796B Ethernet chip. Read/write word access only. This is a mirror of the previous area that does NOT use byte-swap: The memory map between $1800-$1FFC is the same as the area $0800-$0FFC with the only difference that bytes are not swapped.
  • $2800-$2FFC: Reserved for USB module. Register-spacing is 4 bytes. Word access only. This area is byte-swapped.
  • $3800-$3FFC: Reserved for USB module. Register-spacing is 4 bytes. Word access only. This area is NOT byte-swapped.
  • $4000-$7FFC: Reserved for USB module control/status register and future expansion.
  • $8000-$83FC: AX88796B Ethernet chip. Longword read access only. Any longword-access to a chip register in this area will be passed as two read accesses from the chip, and passed as a properly-aligned longword to the host system. This will speed up transfers substantially, especially in Z3 operation. This register area is byte-swapped and uses 0-wait state if the card is in Z3 mode. CAUTION: Experimental! Using this register area requires a higher clock rate than the std. 50MHz on the X-Surf-100. Any higher frequency than 56MHz will violate write access timing.
  • $8400-$87FC: reserved, do not use.
  • $8800-$8BFC: AX88796B Ethernet chip. Longword read access only. Any longword-access to a chip register in this area will be passed as two read accesses from the chip, and passed as a properly-aligned longword to the host system. This will speed up transfers substantially, especially in Z3 operation. This register area is byte-swapped and uses 1 wait state if the card is in Z3 mode.
  • $8C00-$8FFC: AX88796B Ethernet chip. Longword write access only. Any longword-access to a chip register in this area will be passed as two write accesses to the chip using the upper data part of the longword for the first write, and the lower half of the longword for the second write. This will speed up transfers substantially, especially in Z3 operation. This register area is byte-swapped.
  • $9000-$9FFC: AX88796B Ethernet chip. Longword access only. Same as above, just without byte-swap. Please mind the separate read/write areas.
  • $A000-$A7FC: Reserved for USB module. Register spacing is 4 bytes. Longword read access only. This area is byte-swapped.
  • $A800-$AFFC: Reserved for USB module. Register spacing is 4 bytes. Longword write access only. This area is byte-swapped.
  • $B000-$B7FC: Reserved for USB module. Register spacing is 4 bytes. Longword read access only. This area is NOT byte-swapped.
  • $B800-$BFFC: Reserved for USB module. Register spacing is 4 bytes. Longword write access only. This area is NOT byte-swapped.
  • $C000-$FFFC: Reserved, do not use.

68030 and data cache

If the X-Surf-100 is installed in a Z3 system with 68(ec)030 processor, data caches of the 68030 must be switched off while the Asix chip is being accessed. In Z2 systems or if the X-Surf-100 is used in Z2 mode (jumper closed), the 68030 caches are disabled for accesses to the X-Surf-100 anyway. 68040 and 68060 systems are not affected, because their MMU table always marks the X-Surf-100 as "not cacheable". 68020 is not affected because it does not have a data cache.

high speed transfers using the Fifo areas

Data ports of the Ethernet chip and the USB chip are mirrored multiple times to consecutive longword-addresses in the longword area above $8000. Artefacts of the Fifo areas can also be accessed in the word-area below $8000, but that's not of any use. The fact that longword-accesses are transformed into two high-speed 16-bit accesses to the respective chips makes a single transfer very fast. Further, the data port(s) of the respective chips are available multiple times at consecutive longword-aligned addresses, which lets programmers use the movem.l command of the 68k processor to transfer data even faster: Transfer rates up to 22.8 MBytes per second have been measured using the movem.l command, where standard longword-moves are limited to 14 MBytes per second.

Since these high transfer rates can only be reached with 0-wait states, you may only get optimal performance by building a slightly more complicated data transfer routine: On some systems, it may be faster to do two 0-wait word accesses than doing a 1-wait longword access. You will then get top speed for your inner copy-loop by reading a total of 16 words and re-arranging them into eight processor registers that you transfer into memory with the movem.l command. Writing into the USB or Ethernet chip is not affected: Writes are always 0-wait.

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