X-Surf-500 registers

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The X-Surf-500 card uses an Asix AX88796B Ethernet chip. It is largely compatible with the classic NE2000 networking chip. Unlike previous networking cards by iComp, the register layout of the chip on the X-Surf-500 is not linear. This is a result of this card being compatible with both the ACA500 and the ACA500plus accelerators, which use a different address line layout on this port. Porting a driver may require a bit more work than just changing a few addresses.

Finding the card

The X-Surf-500 does NOT use Autoconfig. It will just appear at address space $ee.0000 to $ef.ffff once it's installed on the accelerator. Before launching a driver, it may be a good idea to identify the chip first. This may be done by checking the chip version register and reading the first few bytes of the internal memory; you should find the MAC address there, which should start with iComp's address space 28:CD:4C:. If you cannot find this, chances are high that an X-Surf-500 is not connected.

Register layout

For your convenience, the following table uses similar colours as in the Asix datasheet. Please refer to chapter 5 "Registers operation" of the AX88796B datasheet for a more detailed description of the register bits.

Register name
Chip reg# Amiga addr Page 0 Page 1 Page 2 Page 3
$00 $ee.0000 CR - command register
$01 $ee.0204 PSTART PAR0 Reserved WFBM0
$02 $ee.0c00 PSTOP PAR1 Reserved WFBM1
$03 $ee.0e04 BNRY PAR2 Reserved WFBM2
$04 $ee.2010 TSR(R) / TPSR(W) PAR3 Reserved WFBM3
$05 $ee.2214 NCR(R) / TBCR0(W) PAR4 Reserved WF10CRC
$06 $ee.2c10 CPR(R) / TBCR1(W) PAR5 Reserved WF32CRC
$07 $ee.2e14 ISR CPR Reserved WFOFST
$08 $ee.4080 CRDA0(R) / RSAR0(W) MAR0 Reserved WFLB
$09 $ee.4284 CRDA1(R) / RSAR1(W) MAR1 Reserved WFCMD
$0a $ee.4c80 reserved(R) / RBCR0(W) MAR2 TFP(R) / Reserved(W) WUCSR
$0b $ee.4e84 reserved(R) / RBCR1(W) MAR3 Chip Version(R) / Reserved(W) PMR
$0c $ee.6090 RSR(R) / RCR(W) MAR4 RCR(R) / Reserved(W) Reserved(R) / REER(W)
$0d $ee.6294 CNTR0(R) / TCR(W) MAR5 TCR(R) / Reserved(W) MISC
$0e $ee.6c90 CNTR1(R) / DCR(W) MAR6 DCR(R) / Reserved(W) GPT0
$0f $ee.6e94 CNTR2(R) / IMR(W) MAR7 IMR(R) / Reserved(W) GPT1
$10 $ee.0060 16-bit Data port
$11 $ee.0264 8-bit Data port
$12 $ee.0c60 IFGS1
$13 $ee.0e64 IFGS2
$14 $ee.2070 MII/EEPROM
$15 $ee.2274 BTCR
$16 $ee.2c70 IFG
$17 $ee.2e74 DSR/BJLC
$18 $ee.40e0 Framesize_low
$19 $ee.42e4 Framesize_high
$1a $ee.4ce0 FCR
$1b $ee.4ee4 MCR
$1c $ee.60f0 CTEPR/VLAN_0
$1d $ee.62f4 VLAN_1
$1e $ee.6cf0 BER
$1f $ee.6ef4 HWAKE/Reset
(multiple) $ee.8440 Fifo area: 4 longwords in a row that can be accessed with movem.l

High-speed transfers

Use the Fifo area to transfer data using long word accesses. The Fifo area gives you four long words (=16 bytes) in a row that can be accessed using the movem.l command. This will speed up transfers substantially, especially on CPUs without instruction cache. Further, using longword-accesses on the Fifo area (instead of the 16-bit data port) on the ACA500plus with an A1200 accelerator will double the speed of transfers, because two high-speed 16-bit transfers will be combined into a single 32-bit access for the A1200 accelerator. This cuts bus load in half.

IRQ considerations

The X-Surf-500 uses IRQ level 2 of the Amiga. While the X-Surf-100 has a single IRQ detection bit, the X-Surf-500 only uses the IRQ status register of the Asix chip to identify if an IRQ comes from the Ethernet chip or not. Since the ISR is within paged registers, you will have to carefully check your IRQ service routine for race conditions on the page bits in the command register (CR): Since INT2 is a shared IRQ that is periodically triggered, the IRQ service routine will flip the register page on every INT2. You therefore need to read the page bit status from CR on entry of your service routine, and restore that value before exit.

Data cache considerations

No special care needs to be taken with regard to data caches. As opposed to the X-Surf-100, which may or may not be configured to an address outside the lower 16MB of the system, the X-Surf-500 is always located at $ee.0000. This address space is exempt from data caches on all known accelerators that work with the ACA500 and ACA500plus.

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